TERRY LIN

(626)465-8327                                      1388 1/2 W 23rd ST. LA, CA, 90007                                        kutailin@usc.edu 

OBJECTIVE

To find an internship/co-op or full-time job related to engineering. 

EDUCATION

University of Southern California, Los Angeles, CA                                                      

Master of Science, Electrical Engineering        GPA: 3.55                                                                    Aug 2007~May 2009

National Central University, Taoyuan, Taiwan

Bachelor of Science, Electrical Engineering      GPA: 3.43                                                                  Sep 2000~Jun 2004 

WORK EXPERIENCE

CAD/Cell Library Engineer, Syntronix Corporation, Hsinchu, Taiwan                                                     Aug 2005~May 2007

  Cell Characterization and Model Generation:

• Defined cell layout guideline. Leaded layout team to build circuit layout.
• Researched tool spec document and implemented circuit characterization.
• Reported chip-tapeout progress and improvement.

  Cell Library Verification and Customer Support:

• Communicated foundry to monitor shuttle schedule and realized chip-tape out before deadlines.
• Released official standard cell version and supported users of front-end team and back-end team.

PROJECTS EXPERIENCE

Digital Circuit:

Troy Word Wide Processor (Verilog, Design Compiler, NCSim):                                                      Sep 2008~Dec 2008

• Designed a CPU to achieve runners-up speed of 350MHz.
• Added forwarding function to solve data hazard and stall function to increase clock frequency.
• Capable of handling arithmetic, shift, logic, and access instructions.

  DDR2 Controller (Verilog, Design Compiler, NCSim):                                                                       Sep 2008~Dec 2008

• Designed a controller with FIFO to communicate with Denali model of 512Mb DDR2SDRAM.
• Capable of executing initialization, block read/write, scalar read/write, refresh action.

Analog Circuit:

Operational Amplifier (Cadence Schematic, Spectre):                                  Jan 2008~May 2008 & Jan 2009~May 2009

• Designed a rail-to-rail input(0.2V~1.6V) folded cascode OP-AMP based on the specification of Maxim’s MAX4352, with 70dB gain, 138MHz Unit Gain BW, and 50° PM under 1.8V±10% voltage supply.
• Designed a folded cascode OP-AMP for ADC, with 90dB gain, 200MHz Unit Gain BW, 50° PM, and 30ns settling time under 1.5V±10% voltage supply.

Analog Digital Converter (Cadence Schematic, Spectre):                                                               Jan 2009~May 2009

• Designed a 100MSPS double-rate 12-bit pipeline ADC.
• Implement dynamic latch, switched-capacitor comparator, and gain-2 residue amplifier.

RF Shunt Peaked Circuit Analysis:                                                                                                      Sep 2008~Dec 2008

• Analyzed a given shunt peaked circuit and accomplished broadbanded, maximally flat magnitude.

Hardware/Sofware:

  Solid State Processing and Integrated Circuit Laboratory:                                                            May 2008~Aug 2008

• Operated fabrication steps including oxidation, photolithography, diffusion, etching, ashing, metallization.

Digital Image Processing (C, Matlab):                                                                                                May 2008~Aug 2008

• Programmed image processing theories including Image Enhancement, Noise removal, Edge Detection, Morphological Processing, Digital Halftoning, Geometric Transform, and Optical Character Recognition.

Undergraduate Project: NCUEE 0.18μm Standard Cell Library (Hspice, Design Compiler)                Jun 2003~Jun 2004 

TECHNICAL SKILLS

Hardware Skill: Memory Card, USB, Camera

Coding Skill: Verilog/VHDL(RTL), Perl, C, Keil C, Html

Operating Systems: Unix, Linux(Red Hat), Windows, Mac

Language: Mandarin, English